> Intel could make its first level caches large enough to make real HLL emulators
If you make the L1 cache larger, it will become slower and will be renamed to "L2 cache". There are physical reasons why the L1 cache is not larger, even though programs written in non-highlevel languages would profit from larger caches (maybe even moreso than HLL programs).
> Right now a plug-in or available FPGA could be of great use in many areas.
FPGAs are very, very HLL-unfriendly, despite lots of effort from industry and academia.
If you make the L1 cache larger, it will become slower and will be renamed to "L2 cache". There are physical reasons why the L1 cache is not larger, even though programs written in non-highlevel languages would profit from larger caches (maybe even moreso than HLL programs).
> Right now a plug-in or available FPGA could be of great use in many areas.
FPGAs are very, very HLL-unfriendly, despite lots of effort from industry and academia.